Senior Staff R&D Design Technology Integration Engineer (WLP, Bump, Die Sort)

Exhibit skill and confidence in working cross-functionally across a matrix organization in a very dynamic and fast-paced environment. Support development of advanced technologies for Si / GaAs backend interconnect, passivation, RDL, bump and flip chip packaging (CPI). Monitor and improve existing processes to improve yield, quality, and throughput, thereby increasing efficiency and product reliability. Support new pioneering singulation development. Utilize expertise in process integration between Fabrication (FAB) facilities and Outsourced Semiconductor Assembly and Test (OSAT) companies to anticipate and address potential integration challenges. In-depth knowledge of Backend-of-the-Line (BEOL) processes, with an additional benefit on experience in photolithography techniques. Conversant with substrate and assembly packaging processes for RF-SiP (Radio Frequency-System in Package) applications. Formulate industry-leading design guidelines which involves a comprehensive approach that incorporates lessons from past failures and acknowledges manufacturing constraints. Create, conduct, and analyze Design of Experiments (DOE) for development activities, especially those that relate to bump/die sort quality, yield and impact on CPI. Interface with foundries and OSATs for direct project management of critical programs. Understand process details, SPC, Control plans, OCAPs, FMEAs, PCN, CARs and Quality metrics. Conduct audits, benchmarking and drive best practice methodologies to proactively prevent quality excursions as the technology ramps. Resolve quality, yield and manufacturing problems with structed methods of problem solving. Lead all aspects technology integration into products, perform technical risk assessment, launch mitigation plans and ensure yield and reliability metrics are met and are in line with product release schedules. Team cross-functionally with, Design, Device process development, Packaging, FEA and global NPI teams to support technology readiness for new products Ensure product readiness for ramp. Protect product integrity post ramp. Master's Degree or equivalent in Mechanical / Materials / Chemical Engineering. PHD Preferred 10+ years of experience desired in electronics packaging in related environments, especially RF module industry At least 5 years direct experience in process engineering, product integration or quality management at tier 1 foundries, or assembly sub-contractors. Solid technical understanding of full range of Semiconductor packaging materials, material interactions, processes, dominant failure mechanisms and analytical techniques. Good knowledge of packaging industry standards (IPC, JEDEC, IEEE, ISO, ANSI). Understanding of package/product qualification and reliability methods and failure analysis is required. Familiarity with PCB design and layout tools preferred. Understanding of statistics, control methodology, FMEA, analytical trouble shooting in a factory environment is required. Excellent communication skills. Willingness to travel internationally, typically once per quarter. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.