ASIC Design Verification Engineer (Security Group)

Work with subsystem and SOC Architects to understand the concepts and high-level system requirements. Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture. Develop Verification Methodology, ensuring scalability and portability across environments. Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Coverpoints. Develop Verification Plans and Testbenches for your functional domain. Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures. Track and report DV progress using a variety of metrics, including Bugs and Coverage. Deep knowledge of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains and clock gating. Solid understand of memory organization, fault-tolerant design, parity schemes, error detection and error correction schemes. Advance techniques such as: Formal, Assertions, and Silicon bring-up, is helpful. In-depth knowledge of Micro-processor functions, Network-on-Chip Architectures, and Micro-architectures. Experience in writing Testplans, portable Testbenches, Transactors, and Assembly code. Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification. Ability to develop and work independently on a Block/Unit of the design. Minimum Experience Level should be 2+ years in SOC-level or core-level verification with good understanding of debugging either ARM-based or RISC-V based processors, good understanding of APB/AHB/AXI protocols. Prior experience in any cryptographic algorithm is preferred. Must have basic understand on UNIX commands and Python/Perl scripting Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.