Senior Engineer, Memory Layout

Ho Chi Minh City, Hồ Chí Minh, Vietnam March 7, 2026 Eightfold Ai

Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow. Tools Cadence Virtuoso/VXL, Calibre verification tools & Calibre RVE. Educational Requirements Bachelor's, Electrical or Electronics Engineering or equivalent Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

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Senior Engineer, Memory Layout

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