Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Bachelor's or Masters degree in Science, Engineering, or related field. 5+ years ASIC design, RTL coding, front-end digital design experience 3-10 years of ASIC design (RTL coding) Preferred Exposure to RTL Design Verification flows is a plus Bachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design Master's degree preferred Experience with the following: LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors On-chip tightly coupled SRAM & L3 cache controller architecture/design Experience with x86 or ARM CPU/bus architectures Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification Required: Bachelor's, Computer Engineering and/or Electrical Engineering Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.