Hardware Debug Senior Engineer

Your responsibilities will include resolving customer-related failures, collaborating with global teams, and providing design and debug recommendations. Execute post-silicon validation for SOC interfaces including Ethernet, PCIe, and USB. HSIO electrical validation across Silicon bring-up, platform enablement, volume data analysis. Coordinate with design, ATE, validation, bench, software and customer Engineering teams for chip bring-up, issue debug, and root cause analysis. Document validation results, track and debug chip issues, and provide optimized settings to software API teams. Execute validation plans, test methodologies, and measurement procedures for Ethernet, PCIe functional validation and high-speed I/Os. Investigate and resolve PCIe, Memory, MCA (Machine Check Architecture), micro-controller, and RAS (reliability, availability, and serviceability) related failures with customers. Collaborate with design, validation, and architecture teams to develop content coverage, test patterns, and debugging strategies. Utilize debug tools (e.g., protocol analyzers, SCAN, and JTAG) to narrow down and root cause customer issues. Travel to development and customer sites as needed to support rack-level solution deployment and validation. Influence and communicate technical recommendations across disciplines and geographic locations. Coordinate and deliver technical training for ODMs, with a focus on rack-level system integration and deployment. Coding skills in scripting languages (Unix, Linux, Python, Perl). Knowing C/C++ is a plus. Ability to read and understand schematics. Hardware debug and analytical skills. Strong communication and collaboration skills to interact with team and across functional teams. Working in lab environment. Experience in post-silicon validation. Experience in high-speed IO interfaces, especially PCI Express protocol. Experience in using lab equipment such as BERT, VNA, scopes, protocol analyzer, signal generator, jtag debugger, etc. Strong collaboration and communication skills for cross-team coordination and customer issue resolution. PCIe functional and protocol (Gen1~Gen5) debug, including PCIe IP bring-up, validation, and analysis. Ethernet functional and protocol validation, debug, and analysis. Memory functional and protocol validation and/or debug. MCA/MCE validation and/or debug. RAS validation and/or debug. Master's degree in computer/electrical engineering, or related field. 5+ yrs. experience in Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.