GPU Physical Design Engineer (Lead/Staff/Sr Staff)
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 6 to 15 years of experience in Physical Design / Physical Implementation for complex SoCs or high‑performance cores (GPU or CPU preferred) Strong hands‑on experience with industry‑standard P&R tools such as Synopsys ICC2 and/or Cadence Innovus Strong expertise in Static Timing Analysis using PrimeTime and/or Tempus Deep understanding of advanced STA concepts and clocking architecture Experience with multi‑corner timing closure and high‑frequency designs Solid understanding of PDN design, power optimization, and leakage control Proficiency in Tcl and/or Perl scripting for flow automation Experience working on advanced deep sub‑micron technology nodes Own complete Physical Design / Physical Implementation flow for complex GPU cores, including: Floorplanning Place and Route Clock Tree Synthesis (CTS) Static Timing Analysis (STA) Physical Verification (DRC/LVS) Formal verification Power Delivery Network (PDN) design Drive timing closure for high‑frequency, data‑path‑intensive GPU blocks across multi‑mode, multi‑corner scenarios Optimize PPA trade‑offs and push designs to aggressive performance and power targets on advanced technology nodes Perform timing ECOs, functional ECO roll‑ins, and debug critical timing, power, and physical violations Collaborate closely with RTL, micro‑architecture, DFT, and signoff teams to resolve constraints, clocking, and implementation issues Develop and apply low‑power implementation techniques and customized P&R strategies for GPU cores Contribute to PD flow automation, methodology improvements, and efficiency enhancements using scripting Mentor junior engineers and provide technical leadership (Staff / Senior Staff levels)
