Data Cache & Coherent Interconnect Architect/Engineer (Multiple Levels)

Architect and design high-performance data cache subsystems and coherent interconnects. Develop performance models and analyze trade-offs in power, area, and latency. Collaborate with cross-functional teams including architecture, RTL, verification, and software. Contribute to the development of new IP blocks and integration into SoC platforms. Apply now to be part of a transformative project at the forefront of computing technology. Strong background in processor architecture and micro-architecture. Hands-on experience with data caches and coherent interconnects. Familiarity with cache coherence protocols (e.g., CHI, ACE, or equivalent). Proficiency in C/C++ and/or Verilog/SystemVerilog. Experience in IP development and performance analysis. Prior experience with CHI protocol or similar. Exposure to SoC integration and system-level performance modeling. Strong analytical and debugging skills. Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 4+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 3+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. 2+ years of experience with high-performance microprocessor design.