AI/ML RTL Engineer

Drive RTL design in SystemVerilog, owning features from concept through tape-out Perform early logic synthesis, static timing analysis, and power estimation to validate design choices before full implementation. Evaluate the design pipeline end‑to‑end—from instruction set architecture through microarchitecture, RTL development, and synthesis feasibility. Utilize industry‑standard digital design tools including simulators, synthesis engines, and power/performance analysis frameworks. Debug, optimize, and enhance EDA tool flows; identify and resolve tool‑related issues to improve design iteration efficiency. Strong hands‑on experience with SystemVerilog and deep understanding of RTL design methodologies. Solid foundation in AI/ML concepts Proficiency in Python, Perl, and shell scripting for design automation and tooling. Experience with Git and other revision control systems. Strong analytical, communication, and cross‑functional collaboration skills. Ability to operate both independently and effectively within a fast‑paced, team‑oriented environment. Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 1+ year of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field. 2+ years of experience with high-performance microprocessor design.