Staff Clock, Reset & Power Architecture Engineer, AI Hardware

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

We are seeking a Staff Clock, Reset & Power Architecture Engineer to lead the clock, reset, and power architecture for next generation SoCs. In this high visibility position you will define scalable multi clock systems, integrate PLL based clock generation, and ensure reliable operation across multiple power and reset domains. You’ll collaborate closely with architecture, RTL, verification, timing, and physical design teams to deliver robust, low power clocking and reset infrastructure that drives performance, power efficiency, and silicon reliability for complex multi domain chips.

• Deliver functional IP blocks into the target SoC, ensuring they meet all architectural and software requirements
• Evaluate existing internal and external IP to understand functionality, interfaces, and integration constraints
• Analyze and optimize timing, performance, power, and area (PPA) across the design
• Diagnose and resolve clock‑tree and reset‑distribution issues to guarantee robust system operation
• Specify, micro‑architect, and RTL‑code accelerators, memory subsystems, and network components
• Balance trade‑offs among functional, physical, and performance targets, making data‑driven decisions
• Partner with cross‑functional teams (implementation, verification, performance engineering) throughout the design flow
• Design for synthesis readiness, adhering to best‑practice coding styles and tool constraints

• 8‑12+ years ASIC/SoC design experience
• Deep expertise in clock architecture, distribution, muxing, dividers and PLL integration
• Proven skill in reset architecture, sequencing and domain‑crossing solutions
• Strong knowledge of CDC, RDC and low‑power design methodologies
• Hands‑on experience with UPF/CPF power‑intent flows and power‑gating strategies
• Proficient in STA constraints, timing closure for multi‑clock designs and clock‑tree synthesis
• Extensive RTL development using Verilog/SystemVerilog and scripting (Python/Tcl/Perl)
• Worked on large multi‑billion‑gate SoCs with DFT considerations for clock/reset
• Familiar with industry tools: CDC/RDC analysis, PrimeTime/Tempus and low‑power verification flows
• Degree in Electrical Engineering, Computer Science, or equivalent experience