NPU/AI Processor Synthesis Staff/ Sr Staff/ Technical Lead

Synthesis Ownership Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows for hierarchical and flat designs. Collaborate with STA teams to resolve setup/hold violations. Apply physical-aware synthesis techniques to meet aggressive PPA targets. Implement low-power strategies using UPF/CPF flows. Work closely with RTL design, DFT, and physical design teams for seamless handoff. Provide feedback to architecture and RTL teams for QoR improvements. Perform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting. Mentor junior engineers and drive best practices across synthesis and timing teams. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Strong knowledge of ASIC design flow: RTL → Synthesis → STA → P&R. Proficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime). Experience with UPF/CPF-based flows and multi-voltage designs. Ability to lead synthesis teams and coordinate with cross-functional groups. Bachelor's/Master's in Electrical Engineering, Computer Engineering, or related field. 15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design. Experience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows. Prior tape-out experience for NPU or DSP cores.