Cellular ASIC Design Engineer – Protocols
Various Locations within San Francisco Bay Area
April 15, 2026
Apple Custom Ats
Summary
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something.
Description
We're looking for a Cellular ASIC Design Engineer, where you will architect and implement protocol processing hardware for next-generation wireless SoCs. You will own the full lifecycle from early architectural exploration and HW/SW partitioning, through RTL implementation, to silicon bring-up and lab validation. You will collaborate closely with software, firmware and verification teams to deliver hardware that balances performance, flexibility, and power efficiency.
Minimum Qualifications
BS and a minimum of 10 years relevant industry experience.
Hands-on expertise in SystemVerilog and Verilog.
Skilled in with synthesis and timing analysis tools.
Experience with low-power design techniques.
Proficiency with AMBA bus protocols (AXI, AHB) or similar on-chip NoCs.
Expertise in designing and optimizing scheduling and QoS mechanisms.
Preferred Qualifications
MS or PhD in Computer Engineering or Electrical Engineering.
Understanding of cellular MAC, WiFi MAC or other data-link layer (L2) protocols.
Solid grasp of IP and TCP/UDP protocols.
Background in network infrastructure architecture (e.g. routers, access points, switches).
Experience with packet buffering, queuing, and scheduling.
Knowledge of security algorithms (AES or similar).
Experienced with scheduling and arbitration designs for memory subsystems.
Developed architectural models in C/C++ or SystemC.
