3DIC Diagnostics Architect, Sr. Staff

Diagnostics Architecture Architect end‑to‑end diagnostics solutions for 3DIC products, spanning wafer test, package-level test, and system-level test. Lead memory diagnostics architecture across SRAM, embedded DRAM, stacked DRAM, and emerging memory technologies. Specify and evolve BIST, BIRA/BISR, redundancy, and repair architecture to support efficient defect screening and yield recovery. Architect TSV and interposer diagnostic flows that emphasize failure signature capture, layer-to-layer isolation, suspect clustering, redundancy utilization, and stress-aware diagnostics. Collaborate with design teams to ensure diagnosability is designed in early, with clear test hooks, observability, and repair options. Guide enhancements to internal and EDA vendor diagnostic tools to support 3DIC‑specific failure modes. Partner closely with DFT, design, test, packaging, and manufacturing teams to ensure diagnostic requirements are understood and adopted. Lead technical deep dives on failure modes, test structures, and diagnosability limitations. Mentor junior engineers and guide the technical direction of diagnostic strategy for next‑generation 3DIC programs. Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's or Ph.D. in Electrical Engineering, Computer Engineering, or related field. Extensive experience in diagnostics, DFT, test methodology, and silicon bring-up. Deep knowledge of memory DFT, BIST, redundancy/repair, and structural test content. Strong understanding of 2.5D/3DIC packaging, TSV/HBM structures, and related failure mechanisms. Proficiency with DFT/diagnostic tools from major EDA vendors. Clear, concise communication skills and demonstrated leadership in complex technical domains. Experience designing or improving BIST/BIRA/BISR flows in advanced SoCs or 3DIC architectures. Background in memory diagnostics across SRAM, embedded DRAM, and stacked DRAM. Familiarity with packaging-induced defect mechanisms and associated test strategies. Experience influencing architecture decisions across multiple cross-functional teams. Ability to incorporate automation or AI-assisted methods selectively to improve diagnostic workflows.